Improvements Intel 80486

the 486dx2 architecture

the instruction set of i486 similar predecessor, intel 80386, addition of few instructions, such cmpxchg implements compare-and-swap atomic operation , xadd, fetch-and-add atomic operation returning original value (unlike standard add returns flags only).

from performance point of view, architecture of i486 vast improvement on 80386. has on-chip unified instruction , data cache, on-chip floating-point unit (fpu) , enhanced bus interface unit. due tight pipelining, sequences of simple instructions (such alu reg,reg , alu reg,im) sustain single clock cycle throughput (one instruction completed every clock). these improvements yielded rough doubling in integer alu performance on 386 @ same clock rate. 16-mhz 80486 therefore had performance similar 33-mhz 386, , older design had reach 50 mhz comparable 25-mhz 80486 part.

differences between i386 , i486

an 8 kb on-chip (level 1) sram cache stores used instructions , data (16 kb and/or write-back on later models). 386 had no such internal cache supported slower off-chip cache (which not level 2 cache because there no internal level 1 cache on 80386).
tightly coupled pipelining completes simple instruction alu reg,reg or alu reg,im every clock cycle (after latency of several cycles). 386 needed 2 clock cycles this.
integrated fpu (disabled or absent in sx models) dedicated local bus; faster algorithms on more extensive hardware in i387, performs floating point calculations faster compared i386+i387 combination.
improved mmu performance.
new instructions: xadd, bswap, cmpxchg, invd, wbinvd, invlpg.

just in 80386, simple flat 4 gb memory model implemented setting segment selector registers neutral value in protected mode, or setting (the same) segment registers 0 in real mode, , using 32-bit offset registers (x86-terminology general cpu registers used address registers) linear 32-bit virtual address bypassing segmentation logic. virtual addresses mapped onto physical addresses paging system except when disabled. (real mode had no virtual addresses.) 80386, circumventing memory segmentation substantially improve performance in operating systems , applications.

on typical pc motherboard, either 4 matched 30-pin (8-bit) simms or 1 72-pin (32-bit) simm per bank required fit 80486 s 32-bit data bus. address bus used 30-bits (a31..a2) complemented 4 byte-select pins (instead of a0,a1) allow 8/16/32-bit selection. meant limit of directly addressable physical memory 4 gigabytes (2 32-bit words = 2 8-bit words).

cite error: there <ref group=lower-alpha> tags or {{efn}} templates on page, references not show without {{reflist|group=lower-alpha}} template or {{notelist}} template (see page).